The present invention generally relates to voltage regulator circuits, and, more particularly, to a circuit for reducing negative glitches in an output signal of a voltage regulator.
Electronic circuits typically include a voltage regulator that regulates a supply voltage and prevents variations in the supply voltage from propagating to the components of the electronic circuits. However, if the load current changes (i.e., when a current step occurs), the voltage of an output signal of the voltage regulator changes and settles at its desired value after a delay, which occurs due to a feedback operation of the voltage regulator. Such instances generally occur during start-up of a component or switching of a component from one power mode to another. Decreases in the operating voltages and increases in the operating speeds of electronic circuits requires the voltage regulator to respond quickly to the load variations.
One technique to overcome the aforementioned problem is to increase the size of a decoupling capacitor of the regulator circuit, but this results in a significant increase in the circuit area.
Another technique to overcome the aforementioned problem involves reducing the transient response time of the voltage regulator by decreasing the delay caused by the feedback operation. However, this requires including more components in the voltage regulator and requires modification of the voltage regulator design. It also increases the complexity of the voltage regulator, and the power consumption.
It would be advantageous to have a better way to reduce glitches in the output signal of the voltage regulator during load variations.